The present invention relates to clock synchronizing circuitry and, more particularly, to clock synchronizing circuitry having a fast tuning circuit and for synchronizing, in a network, a clock signal to be generated in a terminal node to a clock signal received from a clock feeding device included in a master node.
It is a common practice with a large scale digital communication network to implement a network synchronizing system with a master-slave scheme. In a master-slave synchronizing system, a master node generates a clock signal with a clock generating device thereof and sends it to a terminal node. The terminal node generates a clock signal based on the received clock thereinside. Conventional clock synchronizing circuitry using the master-slave scheme has a phase difference detector for producing a voltage signal representative of a phase difference between an input and an output clock signal, a low pass filter, and a voltage controlled oscillator (VCO) for producing a predetermined clock signal matching the voltage signal. The problem with such clock synchronizing circuitry is as follows. The frequency of the output clock signal is controlled on the basis of the phase difference between an input and an output clock signal. Hence, when the frequency of the input clock signal, which is the reference, is changed or shut off for a moment due to jitter or similar cause, the phase difference detector detects the change or shut-off and feeds the resulting output thereof to the VCO as a phase difference signal. As a result, the VCO outputs a clock signal proportional to the change in the frequency of the input clock signal. Moreover, in an application of the kind requiring a stable output clock signal, uncontrollable phase deviations occur because the output clock signal is controlled on the basis of a variation width produced by a temperature compensation circuit which is included in the VCO.
U.S. patent application Ser. No. 08/186,522 filed Jan. 26, 1994, now U.S. Pat. No. 5,475,325 issued on Dec. 12, 1995 which is incorporated herein by reference, has proposed clock synchronizing circuitry with an implementation for eliminating the above problems, as follows. .Assume that at the time when the circuitry is reset due to power-on, i.e., when it is started up, an input clock fin has a frequency noticeably deviated from the center frequency of a VCO 5. Then, the circuitry sequentially tunes the VCO 5 to the input clock fin by using control amounts A and B set in a frequency phase control circuit 3. The control amounts A and B are of such a degree that they do not cause errors to occur in the following system. As a result, a long tuning time is required after the start-up of the circuitry. This increases the period of time necessary for a terminal node, forming a synchronous network based on an output clock f.sub.out, to become operable stably.